1. Field of the Invention
This invention relates to a semiconductor device and a method of manufacturing the same, and more particularly relates to an electric power semiconductor device having a high withstand voltage structure, and a method of manufacturing the same.
2. Description of the Related Art
Development of electric power semiconductor devices including high withstand voltage structures is in progress. Such a high withstand voltage structure often includes a power MOSFET (metal oxide semiconductor field effect transistor). With the foregoing electric power semiconductor device, a withstand voltage at a peripheral area of an element area of a substrate is designed to be higher than a withstand voltage at the element area of the substrate where the power MOSFET is arranged. A RESURF (reduced surface field) structure is used at the peripheral area of the substrate.
With the RESURF structure, when a reverse bias is applied, a depletion layer extends from the element area to the periphery thereof in order to improve the withstand voltage. The semiconductor device having the RESURF structure can realize a high withstand voltage in a relatively small space compared with a semiconductor device having the FLR structure. In other words, the RESURF structure can improve an integration degree of the electric power semiconductor device.
In the power MOSFET, an n type epitaxial layer on an n type silicon single crystal substrate is used as a drain region, a p type body layer is placed on the drain region, and an n type source region is formed on the p type body layer. A gate insulating film is formed on the p type body layer, and a gate electrode is formed on the gate insulating film. A RESURF layer having the RESURF structure is constituted by the p type semiconductor region on the n type epitaxial layer.
U.S. Pat. No. 5,801,418 discloses one example of electric power semiconductor devices having the RESURF structure.
Electric power semiconductor devices of the related art seem to suffer from the following problems. In the electric power semiconductor device having the withstand voltage structure, a density of impurities in an n type epitaxial layer is designed to be low compared with a density of impurities in a p type body layer. In order to balance charges in the n type epitaxial layer and the p type body layer, a density of impurities in a RESURF layer (p type semiconductor region) having the RESURF structure is designed to be low. In other words, the RESURF layer and the p type body layer of the power MOSFET cannot be produced in the same manufacturing process. Therefore, in the semiconductor device manufacturing process, the RESURF layer is manufactured in a process separate from a p type body layer manufacturing process. Further, if a front (upper) surface of the RESURF layer undergoes metallic contamination, a junction depth of the RESURF layer should be designed to be somewhat large in order to prevent a precipitous decrease of balances of charges which are stored on longitudinal vertical section of the n type epitaxial layer and the p type body layer. For this purpose, an additional diffusion process is required at a high temperature and for long hours in the RESURF layer manufacturing process in order to accomplish a sufficient junction depth. Addition of such a hot and long diffusion process may inevitably increase a manufacturing cost of the electric power semiconductor device.